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h anb it h dd16m72d9w url : www.hbe.co.kr 1 hanbit electronics co.,ltd. rev 1.0 (november.2002) general description th e HDD16M72D9W is a 64 m x 72 bit double data rate(ddr) synchronous dynamic ram high - density memory module. the module consists of nine cmos 16 m x 8 bit with 4banks ddr sdram s in 66pin tsop - ii 400mil package s and 2k eeprom in 8 - pin tssop package on a 184 - pin glass - epoxy. four 0. 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the HDD16M72D9W is a di mm ( dual in line memory module ) . synchronous design allows precise cycle control wit h the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications . a ll module components may be powered from a single 2.5 v dc power supply and all inputs and outputs are sstl_2 compatible. features ? p art identification HDD16M72D9W C 10a : 1 00 mhz (cl= 2 ) HDD16M72D9W C 13a : 1 33 mhz (cl= 2 ) HDD16M72D9W C 13b : 1 33 mhz (cl= 2.5 ) ? power supply : v dd : 2.5v 0.2v, v ddq : 2.5v 0.2v ? double - data - rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck) ? dll aligns dq a nd dqs transition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 15.6 us re fresh interval ( 4 k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1 200 mil, double sided component ddr sdram module 128mbyte (16mx72bit), based on 16mx8, 4banks 4k ref., 184pin - dimm with unbuffered ecc part no . h dd16m72d9w
h anb it h dd16m72d9w url : www.hbe.co.kr 2 hanbit electronics co.,ltd. rev 1.0 (november.2002) pin assignment *these pins should be nc in the system which does not support spd pin pin description pin pin description a0~a11 address input vdd power supply(2.5v) ba0~ba1 bank select address vddq power supply for dqs(2.5v) dq0~dq63 data input/output vref power supply for reference cb0~cb7 check bit(data input/output ) vspd serial eeprom power supply(3.3) dqs0~dqs7 data strobe input/output vss ground dm0~dm7 data - in mask sa0~sa2 address in eeprom ck0~ck2,/ck0~/ck2 clock input sda serial data i/o cke0 clock enable input scl serial clock /cs0 chip select input wp wr ite protection /ras row address strobe vddin vdd identification flag /cas column address strobe nc no connection pin front pin back pin frontl pin back pin front pin back 1 vref 32 a5 62 v ddq 93 v ss 124 v ss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 v ss 34 v ss 64 dq41 95 dq5 126 dq28 156 v ddq 4 dq1 35 dq25 65 /cas 96 v ddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 v ss 97 dm0 128 v ddq 158 * /cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 v dd 38 v dd 68 dq42 99 dq 7 130 a3 160 v ss 8 dq3 39 dq26 69 dq43 100 v ss 131 dq30 161 dq46 9 nc 40 dq27 70 v dd 101 nc 132 v ss 162 dq47 10 nc 41 a2 71 * /cs2 102 nc 133 dq31 163 * /cs3 11 v ss 42 v ss 72 dq48 103 nc 134 cb4 164 v ddq 12 dq8 43 a1 73 dq49 104 v ddq 135 cb5 165 dq52 13 dq9 44 cb0 74 v ss 105 dq12 136 v ddq 166 dq53 14 dqs1 45 cb1 75 * ck2 106 dq13 137 ck0 167 *a13 15 v ddq 46 v dd 76 * /ck2 107 dm1 138 /ck0 168 v dd 16 * ck1 47 dqs8 77 v ddq 108 v dd 139 v ss 169 dm6 17 * /ck1 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 v ss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 v ss 80 dq51 111 cke1 142 cb6 172 v ddq 20 dq11 51 cb3 81 v ss 112 v ddq 143 v ddq 173 nc 21 cke0 52 ba1 82 vddid 113 * ba2 144 cb7 174 dq60 22 v ddq key 83 dq56 114 dq20 key 175 dq61 23 dq16 53 dq32 84 dq57 115 *a12 145 v ss 176 v ss 24 dq17 54 v ddq 85 v dd 116 v ss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 v ss 56 dqs4 87 dq58 118 a11 148 v dd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 v ddq 28 dq18 58 v ss 89 v ss 12 0 v dd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 v ddq 60 dq35 91 sda 122 a8 152 v ss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd
h anb it h dd16m72d9w url : www.hbe.co.kr 3 hanbit electronics co.,ltd. rev 1.0 (november.2002) f unctional block diag ram
h anb it h dd16m72d9w url : www.hbe.co.kr 4 hanbit electronics co.,ltd. rev 1.0 (november.2002) pin function description pin name input function ck, / ck clock ck and / ck are differential clock inputs. all address and control input signals are sampled on the positive edge of ck and negative edge of ck. output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck. cke clock enable cke high activates, and cke low dea ctivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power - down and self refresh operation (all banks idle), or active power - down(row active in any bank). cke is synchronous for all functio ns except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power - down and self refresh modes, providing low standby power. cke will recognize an lvcmos low level prior to vref being stable on power - up. /cs chip select / cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when / cs is registered high. / cs provides for external bank selection on systems with multiple banks. / cs is considered par t of the command code. a0 ~ a1 1 address a ddresses are multiplexed on the same pins. a ddress : a0 ~ a1 1 ba0 ~ ba1 bank select address b a0 and ba1 define to which bank an active, read, write or pre - charge command is being applied. / ras row address strobe latches row addresses on the positive going edge of the clk with / ras low. enables row access & precharge. / cas columnaddress strobe latches column addresses on the positive going edge of the clk with / cas low. enables column access. / we write enable ena bles write operation and row precharge. latches data in starting from / cas, / we active. dq s 0 ~ 7 data strobe output with read data, input with write data. edge - aligned with read data, cen - tered in write data. used to capture write data. dm0~7 input dat a mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load - in g. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. wp write protection wp pin is connected to vcc. when wp is high , eeprom programming will be inhibited and the entire memory will be write - protected. vddq supply dq pow er supply : +2.5v 0.2v. vdd supply power supply : +2.5v 0.2v (device specific). vss supply dq ground. vref supply sstl_2 reference voltage.
h anb it h dd16m72d9w url : www.hbe.co.kr 5 hanbit electronics co.,ltd. rev 1.0 (november.2002) absolute maximum rat ings parameter symbol rating unte voltage on any pin relative to vss v in , v out - 0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd - 1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq - 0.5 ~ 3.6 v storage temperature t stg - 55 ~ +150 c power dissipation p d 13.5 w short circuit current i os 50 ma notes: permanent device damage m ay occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. power & dc operating con ditions ( recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) ) parameter symbol min max unit note supply voltage v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref v ddq /2 - 50mv v ddq /2+50mv v 1 i/o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 2 input high voltage v ih (dc) v ref + 0.15 v ref + 0.3 v input low voltage v il (dc) - 0.3 v ref - 0.15 v input voltage level, ck and /ck inputs v in (dc) - 0.3 v ddq + 0.3 v input differential voltage , ck and /ck inputs v id (dc) 0.3 v ddq + 0.6 v input leakage current i l i - 2 2 ua 3 out put leakage current i oz - 5 5 ua out put high current (v out = 1.95v) i oh - 16.8 ma out put low current (v out = 0.35v) i o l 16.8 ma output high current(h alf strengh driver) i oh - 9 ma output high current(half strengh driver) i ol 9 ma notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de - coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc le vel of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a v ref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the same. 6. these charactericteristic s obey the sstl - 2 class ii standards.
h anb it h dd16m72d9w url : www.hbe.co.kr 6 hanbit electronics co.,ltd. rev 1.0 (november.2002) input/output capacitance ( v dd = 2.5v , v ddq = 2.5v , t a = 2 5 c, f = 1mhz ) description symbol min max units input c apacitance( a0 ~ a1 2, b a0 ~ b a1 ,ras,cas, we ) c in1 49 57 pf input c apacitance(ck e 0) c in2 42 50 pf input c apacitance( c s 0) c in3 42 50 pf input c apacitance( cl k 0, cl k 1 ,cl k 2 ) c in4 22 25 pf data & dqs input/output c apacitance(d q 0~d q6 3) c out1 6 8 pf input c apacitance(d m 0~d m 8) c in5 6 8 pf ac operating conditions parameter/ condition s tmbol min max unit note input high (logic 1) voltage, dq, dqs and dm s ignals v ih (ac) v ref + 0.31 3 input low (logic 0) voltage, dq, dqs and dm signals. v il (ac) v ref - 0.31 v 3 input differential voltage, ck and ck inputs v id (ac) 0.7 v ddq +0.6 v 1 input crossin g point voltage, ck and ck inputs v ix (ac) 0.5*v ddq - 0.2 0.5*v ddq +0.2 v 2 note 1. v id is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and m ust track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specificatims are refation to a v ref envelope that ha s been bandwidth limited 20mhz. ac operating test conditions parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 0.5 v/ns input levels( v i h / v i l ) v re f +0.31/ v re f - 0.31 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit v
h anb it h dd16m72d9w url : www.hbe.co.kr 7 hanbit electronics co.,ltd. rev 1.0 (november.2002) ac timming parameters & specifications (these ac charicteristics were tested on the c omponent) ddr200 ddr266a ddr266b - 10a - 13a - 13b parameter symbol min max min max min max unit note row cycle time t rc 70 65 65 ns 1 refresh row cycle time t rfc 80 75 75 ns 1,2 row active time t ras 48 120k 45 120k 45 120k ns 1,2 / ras to / cas delay t rcd 20 20 20 ns 3 row precharge time t rp 20 20 20 ns 3 row active to row active delay t rrd 15 15 15 ns 3 write recovery time t wr 15 15 15 t ck 3 last data in to read command t cdlr 1 1 1 t ck 2 col. address to col. address dela y t ccd 1 1 1 t ck cl=2.0 10 12 7.5 12 10 12 ns clock cycle time cl=2.5 t ck 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs - out access time from ck/ck t dqsck - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns output data access time from ck/ck t ac - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns data strobe edge to ouput data edge t dqsq - +0.6 - +0.5 - +0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read pos tamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck data out high impedence time from ck - /ck t hzq - 0.8 +0.8 - 0.75 +0.75 - 0.75 +0.75 ns 2 ck to valid dqs - in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs - in setup time t wpres 0 0 0 ns 3 dqs - in hold time t wpreh 0. 25 0.25 0.25 t ck dqs - in falling edge to ck rising - setup time t d ss 0.2 0.2 0.2 t ck dqs - in falling edge to ck rising hold time t dsh 0.2 0.2 0.2 t ck dqs - in high level width t dqsh 0.35 0.35 0.35 t ck dqs - in low level width t dqsl 0.35 0.35 0.35 t ck dqs - in cycle time t dsc 0.9 1.1 0.9 1.1 0.9 1.1 t ck address and control input setup time t is 1.1 0.9 0.9 ns address and control input hold time t ih 1.1 0.9 0.9 ns mode register set cycle time t mrd 16 15 15 ns dq & dm setup time to dqs t ds 0.6 0.5 0.5 ns dq & dm hold time to dqs t dh 0.6 0.5 0.5 ns dq & dm input pulse width t dipw 2 1.75 1.75 ns power down exit time t pdex 10 7.5 7.5 ns exit self refresh to write command t xsw 116 95 ns exit self refresh to b ank active command t xs a 80 75 75 ns exit self refresh to read command t xs r 200 200 200 cycle refresh interval time t ref 15.6 15.6 15.6 us 1 output dqs valid window t q h - - - - - - t ck dqs write postamble time t w pst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 4
h anb it h dd16m72d9w url : www.hbe.co.kr 8 hanbit electronics co.,ltd. rev 1.0 (november.2002) notes : 1. maximum burst refresh cycle : 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a pre vious write was in progress, dqs could be high at this time, depending on t dqss . 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degra de accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter ( t jit (hp) ) of the pll and the half jitter due to crosstalk ( t ji t (crosstalk) ) on the dimm. 6. input setup/hold slew rate derating input setup/hold slew rate t is t ih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 - this derating table is used to increase t d s / t dh in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac - ac slew rate and dc - dc slew rate. 7. i/o setup/hold slew rate derating input setup/hold slew rate t is t ih (v/ns) (ps) (ps) 0.5 0 0 0.4 + 75 + 75 0.3 + 150 + 150 - this derating table is used to increase t d s / t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac - ac slew rate and dc - dc slew rate. 8. i/ o setup/hold plateau derating i/o input level t ds t dh (mv) (ps) (ps) 280 +50 +50 - this derating table is used to increase t d s / t dh in the case where the input level is flat below v ref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/sl ew - rate) derating delta rise/fall rate t ds t dh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 - this derating table is used to increase t d s / t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1 - 1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate = - 0/5ns/v. input s/h slew rate based on larger of ac - ac delta rise/fall rate and dc - dc delta rise/fall rate. 10. this parameter is fir system simulation pu rpose. it is guranteed by design. 11. for each of the terms, if not already an integer, round to the next highest integer. t ck is actual to the system clock cycle time.
h anb it h dd16m72d9w url : www.hbe.co.kr 9 hanbit electronics co.,ltd. rev 1.0 (november.2002) command truth table (v=valid, x=don t care, h=logic high, l=logic low) command ck e n - 1 cke n /cs /ras /cas /we dm ba 0,1 a10/ ap a11 a9~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & r ow a ddr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge e able h x l h l h x v h column address (a0 ~ a 9 ) 4 auto precharge disable h l 4 write & column address auto precharge en able h x l h l l x v h column address (a0 ~ a 9 ) 4,6 burst stop h x l h h l x x 7 bank selection v l precharge all banks h x l l h l x x h x 5 h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dm h x v x 8 h x x x no operation command h x l h h h x x note : 1. op code : operand code. a0 ~ a12 & b a0 ~ b a1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precha rge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. b a0 ~ b a1 : bank select addresses. if both b a0 and b a1 are "low" at read, write, row active and precharge, bank a is selected. if b a0 is "high" and b a1 i s "low" at read, write, row active and precharge, bank b is selected. if b a0 is "low" and b a1 is "high" at read, write, row active and precharge, bank c is selected. if both b a0 and b a1 are "high" at read, write, row active and precharge, bank d is select ed. 5. if a 10/ap is "high" at row precharge, b a0 and b a1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data - in are masked at the both edges (write dm latency is 0). 9. this co mbination is not defined for any function, which means "no operation(nop)" in ddr sdram.
h anb it h dd16m72d9w url : www.hbe.co.kr 10 hanbit electronics co.,ltd. rev 1.0 (november.2002) package dimensions unit : mm < front C side > < rear C side > 133.35 0.20
h anb it h dd16m72d9w url : www.hbe.co.kr 11 hanbit electronics co.,ltd. rev 1.0 (november.2002) o r dering information part number density org. package ref. vcc mode max.frq hdd16m72d9 w - 10a 128mbyte 16m x 72 184pin dimm 4k 2.5v ddr 100mhz/cl2 HDD16M72D9W - 13a 128mbyte 16m x 72 184pin dimm 4k 2.5v ddr 133mhz/cl2 HDD16M72D9W - 13b 128mbyte 16m x 72 184pin dimm 4k 2.5v ddr 133mhz/cl2.5

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